`timescale 1ns/100ps 

module tb_onu_mac();
reg 			  hresetn, hclk;
wire 	  [31:0]  haddr;
wire 	  [1:0]   htrans;
wire 		   	  hwrite;
wire 	  [2:0]   hsize;
wire 	  [2:0]   hburst;
wire 	  [3:0]   hprot;
wire 	  [31:0]  hwdata;

wire 		   	  hready;		//input
wire  	  [1:0]   hresp;
wire  	  [31:0]  hrdata;
//APB
reg 		   	  presetn;
reg 		   	  pclk;
reg 		   	  psel;
reg 		   	  penable;
reg 		   	  pwrite;
reg  	  [31:0]  paddr;
reg  	  [31:0]  pwdata;
wire 	  [31:0]  prdata;


wire 		   	  Tx_en, Tx_er;
wire 	  [7:0]   Txd;
wire 		   	  Rx_dv, Rx_er;
wire  	  [7:0]   Rxd;
wire 		   	  Rx_clk;						//from PHY
reg 		   	  Gtx_clk;						//connect to RS, not from PHY	
wire 		   	  Col, Crs;

onu_mac U_onu_mac(
	//host interface
	//AHB
	.hresetn				(hresetn),
	.hclk					(hclk),
	.haddr					(haddr),
	.htrans					(htrans),				//how about sel ??
	.hwrite					(hwrite),
	.hsize					(hsize),
	.hburst					(hburst),
	.hprot					(hprot),
	.hwdata					(hwdata),
	.hready					(hready),
	.hresp					(hresp),
	.hrdata					(hrdata),
	
	//APB
	.presetn				(presetn),
	.pclk					(pclk),
	.psel					(psel),
	.penable				(penable),
	.pwrite					(pwrite),
	.paddr					(paddr),
	.pwdata					(pwdata),
	.prdata					(prdata),

	//interface for PHY : GMII 
	.Tx_en					(Tx_en), 
	.Tx_er					(Tx_er),
	.Txd					(Txd),
	.Rx_dv					(Rx_dv),
	.Rx_er					(Rx_er),
	.Rxd					(Rxd),
	.Rx_clk					(Rx_clk),				//from PHY
	.Gtx_clk				(Gtx_clk),				//connect to RS, not from PHY	
	.Col					(Col), 
	.Crs					(Crs)
);

////////////////////////////////////////////////////////////////////////////////////////////////////
// interface for AHB  (ram : AHB Slave)
wire 			  hsel;
assign 			  hsel 		  = 1'b1;
ahb_ram_if U_ahb_ram(
	.hresetn				(hresetn),
	.hclk					(hclk),
	.hsel					(hsel),	
	.haddr					(haddr),
	.htrans					(htrans),
	.hwrite					(hwrite),
	.hsize					(hsize),
	.hburst					(hburst),
	.hprot					(hprot),
	.hwdata					(hwdata),
	
	.hready					(hready),
	.hresp					(hresp),
	.hrdata					(hrdata) 
);

initial begin
  hclk = 0;
  forever #3 hclk = ~hclk;
end

initial begin
  hresetn = 0;
  #10 hresetn = 1;
end
////////////////////////////////////////////////////////////////////////////////////////////////////
// interface of APB Bridge for PLI
always@(posedge pclk or negedge presetn)
begin
  if(!presetn)
	#1 $apb_bridge_reset();
  else
	#1 $apb_bridge(psel, penable, pwrite, paddr, pwdata, prdata);
end

initial begin
  presetn = 0;
  #200 presetn = 1;
end

initial begin
  pclk = 0;
  forever #20 pclk = ~pclk;
end
////////////////////////////////////////////////////////////////////////////////////////////////////
// interface for PHY
onu_phy U_onu_phy(
	.Gtx_clk				(Gtx_clk)				, //used only in GMII mode
	.Tx_en 					(Tx_en)					,
	.Tx_er 					(Tx_er)					,
	.Txd					(Txd)					,
	
	.Rx_clk					(Rx_clk)					,
	.Rx_dv					(Rx_dv)					,
	.Rx_er					(Rx_er)					,
	.Rxd					(Rxd)					,
	
	.Col					(Col)						,	
	.Crs					(Crs)						
	);
////////////////////////////////////////////////////////////////////////////////////////////////////
// Gtx_clk, connect to RS
initial begin
  Gtx_clk = 0;								//this signal should supplied by the Reconciliation Sublayer !
  forever #4 Gtx_clk = ~Gtx_clk;			//125M
end
////////////////////////////////////////////////////////////////////////////////////////////////////
endmodule // tb_onu_mac



